How To Loop With Registers

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[SOLVED] Verilog Loop performance with registers.

• Thread starter ismailov-due east
• Showtime engagement January 26, 2015

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• #1

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Hi
Who can help me please.
I want to brand some loop performance. for example: utilize loop in register indexes

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Code Verilog -                                            [aggrandize]                                          
                                        
                                      
                                      
                                        
                                          
                                            
one ii 3 4 5 vi 7 eight 9 10 11 12 13 fourteen 15 16 17 18 nineteen 20 21 22                                            
                                          
                                          
                                            
                                              reg                                              [                                              vii                                              :                                              0                                              ]                                              res;                                              reg                                              [                                              7                                              :                                              0                                              ]                                              buff                                              for                                              (i                                              =                                              0                                              ;                                              i                                              <                                              8                                              ;                                              i                                              =                                              i                                              +                                              1                                              )                                              res                                              <=                                              vitrify[i+                                              1                                              :i]                                              +                                              i;                                              module                                              integers(                                              clock,                                              res                                              )                                              ;                                              input                                              clock;                                              output                                              res;                                              wire                                              clock;                                              reg                                              [                                              vii                                              :                                              0                                              ]                                              res;                                              reg                                              [                                              seven                                              :                                              0                                              ]                                              buff                                              =                                              0                                              ;                                              genvar                                              i;                                              for                                              (i                                              =                                              0                                              ;                                              i                                              <                                              viii                                              ;                                              i                                              =                                              i                                              +                                              i                                              )                                              brainstorm                                              e'er                                              @                                              (                                              negedge                                              clock)                                              begin                                              res                                              <=                                              vitrify                                              +                                              i;                                              end                                              terminate                                            
                                          
                                        
                                      
                                    
                                  
                                

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information technology outputs only 1. but should counts.

Last edited past a moderator: Jan 26, 2015

• #2

You lot're misunderstanding loops. They are for generating parallel logic not a sequence in time. Output res can be simply driven past i source, the shown code should give a multiple drivers error.

- specify what y'all exactly want to accomplish
- read a Verilog text volume or tutorial
- write a code that complies with Verilog syntax rules
- come back with specific questions most your design, if any

• #three

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Actually i wrote separate lawmaking. Just it seems merged.
For example i have a viii-bit annals "res [seven:0]". Allow say i want to discover positive value in each $.25 in this register. Count positive bits.

• #4

Actually i wrote separate lawmaking. But it seems merged.
For example i take a 8-fleck register "res [7:0]". Allow say i desire to find positive value in each bits in this register. Count positive $.25.

This kind of question can easily be looked up by you. Why make u.s. do it. I plant a postal service on edaboard that discusses this.

Use the advanced search and look for a mail called "Count the number of 1's" as the title of the mail.

• #five

What kind of "loop" do you desire? Basically two options:

1 - Do you want something that loops in time?
ii - Do you want to unroll logic, so that you get multiple pieces of logic that execute simultaneously next (loop in infinite)?

Pick 1) is typically what people desire. And so they try (and fail) to employ the loop keyword in verilog for that. This is precisely Not how it works.

When y'all use the loop construct in verilog you really get option 2.

So, repeat after me: loop in verilog does Non loop temporally. loop in verilog loops spatially.

If you want something that loops in time yous should use a counter.

If I look at your code you are already ahead of a large number of the "Don't know what looping does" oversupply, because yous do some things right. Buuuut there'due south as well a few problems with information technology.

It would assistance if you tin can clearly state what your requirements are:

Should it produce a issue every clock cycle? Or is it allowed to produce a result every 8th bike for example.
What does "Count positive bits." mean exactly? I suspect you want to find the number of $.25 that is set to value of 1, but not 100% sure.

Then practise you desire something like this?

input ==> output
8'b00000000 => 0
8'b00010000 => 1
8'b10000000 => i
8'b00100110 => 3
8'b11111111 => 8
...
etc

• #6

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ok guys. i have this code:

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Code Verilog -                                            [expand]                                          
                                        
                                      
                                      
                                        
                                          
                                            
1 ii 3 4 5 6 seven 8 9 10 11 12 13 xiv xv sixteen 17 xviii nineteen                                            
                                          
                                          
                                            
                                              module                                              integers(                                              clock,                                              res                                              )                                              ;                                              input                                              clock;                                              output                                              res;                                              wire                                              clock;                                              reg                                              [                                              7                                              :                                              0                                              ]                                              res;                                              reg                                              [                                              7                                              :                                              0                                              ]                                              buff                                              =                                              0                                              ;                                              genvar                                              i;                                              for                                              (i                                              =                                              0                                              ;                                              i                                              <                                              8                                              ;                                              i                                              =                                              i                                              +                                              i                                              )                                              begin                                              :                                              exam                                              always                                              @                                              (                                              negedge                                              clock)                                              brainstorm                                              vitrify[i]                                              <=                                              1                                              ;                                              res                                              <=                                              buff;                                              finish                                              stop                                              endmodule                                            
                                          
                                        
                                      
                                    
                                  
                                

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For each clock сycle information technology should output:
res = 00000001
res = 00000011
res = 00000111
.
till
res = 11111111
but it outputs:
everytime
res =1111111
information technology seem it shows last count. complete loop then outputs. Not every clock сycle.
what i want is:
buff <= ane;
when i = one
buff[i] = i
and outputs = 00000001
fist bit to prepare one;
then
buff[2] = i e.t.c

- - - Updated - - -

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Code Verilog -                                                [expand]                                              
                                            
                                          
                                          
                                            
                                              
                                                
one 2 iii                                                
                                              
                                              
                                                
                                                  module                                                  integers(                                                  clock,                                                  res                                                  )                                                  ;                                                  input                                                  clock;                                                
                                              
                                            
                                          
                                        
                                      
                                    

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I succed it with this code: Just i wanted to try how loop operation can handle that.

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Code Verilog -                                                [expand]                                              
                                            
                                          
                                          
                                            
                                              
                                                
i 2 iii iv 5 6 7 8 9 10 11 12 13 14 15                                                
                                              
                                              
                                                
                                                  output                                                  res;                                                  wire                                                  clock;                                                  reg                                                  [                                                  7                                                  :                                                  0                                                  ]                                                  res;                                                  reg                                                  [                                                  7                                                  :                                                  0                                                  ]                                                  vitrify                                                  =                                                  0                                                  ;                                                  reg                                                  [                                                  7                                                  :                                                  0                                                  ]                                                  count                                                  =                                                  0                                                  ;                                                  genvar                                                  i;                                                  //for (i = 0; i < viii ; i = i + 1) begin: test                                                  always                                                  @                                                  (                                                  negedge                                                  clock)                                                  begin                                                  count                                                  <=                                                  count                                                  +                                                  i                                                  ;                                                  buff[count]                                                  <=                                                  1                                                  ;                                                  res                                                  <=                                                  buff;                                                  end                                                  //end                                                
                                              
                                            
                                          
                                        
                                      
                                    

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Terminal edited by a moderator: Jan 27, 2015

• #7

Every bit suspected. I repeat the repeat after me role...

So, repeat afterwards me: loop in verilog does Non loop temporally. loop in verilog loops spatially.

If you want something that loops in time you lot should use a counter.

It's a mutual enough mistake, and then no shame there. But it does aid to read replies.

What yous fabricated there is 8 always blocks that exist and execute in parallel. I'll mail service the equivalent to help understand what's going on.

Your lawmaking:

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Lawmaking Verilog -                                        [expand]                                      
                                    
                                  
                                  
                                    
                                      
                                        
1 2 3 4 5 6 7 8 nine 10 xi 12 13 14 15 16 17                                        
                                      
                                      
                                        
                                          module                                          integers(                                          clock,                                          res)                                          ;                                          input                                          clock;                                          output                                          res;                                          wire                                          clock;                                          reg                                          [                                          7                                          :                                          0                                          ]                                          res;                                          reg                                          [                                          vii                                          :                                          0                                          ]                                          vitrify                                          =                                          0                                          ;                                          genvar                                          i;                                          for                                          (i                                          =                                          0                                          ;                                          i                                          <                                          viii                                          ;                                          i                                          =                                          i                                          +                                          1                                          )                                          begin                                          :                                          test                                          always                                          @                                          (                                          negedge                                          clock)                                          brainstorm                                          buff[i]                                          <=                                          1                                          ;                                          res                                          <=                                          buff;                                          end                                          end                                          endmodule                                        
                                      
                                    
                                  
                                
                              
                            

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Equivalent code with the generate loop explicitely unrolled:

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Code Verilog -                                        [expand]                                      
                                    
                                  
                                  
                                    
                                      
                                        
1 ii 3 4 5 6 7 8 9 ten 11 12 xiii xiv 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30                                        
                                      
                                      
                                        
                                          module                                          integers(                                          clock,                                          res)                                          ;                                          input                                          clock;                                          output                                          res;                                          wire                                          clock;                                          reg                                          [                                          7                                          :                                          0                                          ]                                          res;                                          reg                                          [                                          7                                          :                                          0                                          ]                                          vitrify                                          =                                          0                                          ;                                          // equivalent for i=0                                          always                                          @                                          (                                          negedge                                          clock)                                          begin                                          buff[                                          0                                          ]                                          <=                                          1                                          ;                                          res                                          <=                                          buff;                                          end                                          // equivalent for i=1                                          always                                          @                                          (                                          negedge                                          clock)                                          begin                                          buff[                                          1                                          ]                                          <=                                          1                                          ;                                          res                                          <=                                          vitrify;                                          end                                          // equivalents for i=2..half-dozen go hither                                          // equivalent for i=seven                                          always                                          @                                          (                                          negedge                                          clock)                                          begin                                          buff[                                          vii                                          ]                                          <=                                          1                                          ;                                          res                                          <=                                          buff;                                          end                                          endmodule                                        
                                      
                                    
                                  
                                
                              
                            

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And equally you can imagine that is equivalent to:

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Code Verilog -                                        [expand]                                      
                                    
                                  
                                  
                                    
                                      
                                        
1 2 3 4 5 6 seven                                        
                                      
                                      
                                        
...                                          // equivalent with all the above always blocks lumped together                                          always                                          @                                          (                                          negedge                                          clock)                                          begin                                          buff                                          <=                                          8'b11111111                                          ;                                          res<=                                          buff;                                          end                                        
                                      
                                    
                                  
                                
                              
                            

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And that is why you get that all ones (8'b11111111) consequence after one clock cycle.

And to repeat the repeated repetition:

If you desire something that loops in time you should utilise a counter.

Promise that clear things up.

PS: Two more modest things. Offset, it mostly gives better results to use spaces instead of tabs when posting code. Four (4) spaces for an indent is a reasonable value IMO. And the other small thing is that it's considered better style to use this kind of module port proclamation:

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Code Verilog -                                        [expand]                                      
                                    
                                  
                                  
                                    
                                      
                                        
1 2 3 4 5 6 7 8 9 x eleven 12                                        
                                      
                                      
                                        
                                          module                                          integers(                                          input                                          clock,                                          // you could comment this, although clock is probably understood well plenty                                          output                                          reg                                          [                                          vii                                          :                                          0                                          ]                                          res// putting a short description of the "res" bespeak here will increment code readability                                          )                                          ;                                          reg                                          [                                          7                                          :                                          0                                          ]                                          buff                                          =                                          0                                          ;                                          ever                                          @                                          (                                          negedge                                          clock)                                          begin                                          buff                                          <=                                          8'b11111111                                          ;                                          res<=                                          vitrify;                                          finish                                          endmodule                                        
                                      
                                    
                                  
                                
                              
                            

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That'due south a bit shorter, and possibly more readable and maintainable.

• #viii

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in this code (count reg) can utilise as index for one bit and works well; but when i want to utilize multiple indexes it shows bug"count is not a constant" I hateful when i wan't to use group of bits instead of lawmaking "buff[count] <= one;" try "buff[count+1:count] <= three;"

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Code Verilog -                                            [expand]                                          
                                        
                                      
                                      
                                        
                                          
                                            
1 2 three 4 5 half dozen 7 8 9 10 11 12 13 14 fifteen xvi 17 18                                            
                                          
                                          
                                            
                                              module                                              integers(                                              clock,                                              res                                              )                                              ;                                              input                                              clock;                                              output                                              res;                                              wire                                              clock;                                              reg                                              [                                              7                                              :                                              0                                              ]                                              res;                                              reg                                              [                                              7                                              :                                              0                                              ]                                              buff                                              =                                              0                                              ;                                              reg                                              [                                              7                                              :                                              0                                              ]                                              count                                              =                                              0                                              ;                                              genvar                                              i;                                              //for (i = 0; i < viii ; i = i + ane) begin: test                                              always                                              @                                              (                                              negedge                                              clock)                                              begin                                              count                                              <=                                              count                                              +                                              i                                              ;                                              vitrify[count]                                              <=                                              1                                              ;                                              res                                              <=                                              buff;                                              stop                                              //end                                            
                                          
                                        
                                      
                                    
                                  
                                

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Final edited by a moderator: Jan 29, 2015

• #ix

I accept no idea what you mean. Can you rephrase the question?

That, and try to actually incorporate suggestions to improve your code readability:
- Your indents are haphazard and all over the place. apply four spaces per indent. Why? Curt version: to the lowest degree amount of trouble, and always works
- Do not put in commented bits of old code, unless these are specific to the problem being discussed. In this instance your two commented lines have nothing to exercise with the residual of information technology.
- Amend to post a consummate module. Now nosotros have to judge what comes subsequently information technology. sometimes relevant, former not.
- And for bonus points yous could use verilog-2001 ANSI style module port declarations, as shown to you in previous posts.

Anyways, main thing is I don't sympathise this... please rephrase:

in this code (count reg) can use equally alphabetize for one fleck and works well; just when i desire to utilise multiple indexes it shows bug"count is not a constant"

• #10

I think the OP is trying to assign a piece.

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Code Verilog -                                        [aggrandize]                                      
                                    
                                  
                                  
                                    
                                      
                                        
1 2                                        
                                      
                                      
                                        
                                          // assign past pairs of indicies [1:0], [3:2], etc                                          buff[                                          2                                          *count                                          +:                                          two                                          ]                                          <=                                          3                                          ;                                        
                                      
                                    
                                  
                                
                              
                            

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• #11

I recollect the OP is trying to assign a slice.

In which case your mistake correcting requirements decoder works better than mine.

• #12

In which case your mistake correcting requirements decoder works meliorate than mine.

Here y'all can buy a new i ;-)

• #13

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ads-ee Thanks a lot.
Y'all have caught exact what i hateful.
One question: is there any sources(books) where i can find such rools.

• #14

One question: is at that place whatever sources(books) where i can observe such rools.

rools? If you mean rules. I found that syntax for chip slicing in the LRM.

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How To Loop With Registers,

Source: https://www.edaboard.com/threads/verilog-loop-operation-with-registers.330775/

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